The present invention relates to improved semiconductor memory devices represented by a DRAM (dynamic random-access memory). More particularly, it relates to an improved semiconductor memory device in which an increase in leakage current resulting from a short circuit between a bit line and a word line during standby, i.e., an increase in power consumption during standby is restrained.
In general, semiconductor memory devices are provided with a large number of precharge circuits for precharging numerous pairs of bit lines to an intermediate potential between a power-source potential and the ground potential, so that during standby, the pairs of bit lines are precharged by the above precharge circuits to the intermediate potential, while a word line is grounded. If there occurs a short circuit between any of the bit lines and the above word line during standby, a large leakage current is allowed to flow from the short-circuited bit line to the ground potential via the word line. The leakage current is termed a standby current, which significantly reduces the production yield of semiconductor memory devices. In a semiconductor memory device driven by batteries, in particular, the leakage current may cause a reduction in lifetime of the batteries.
To reduce the standby current, there can be devised an arrangement in which a large number of precharge circuits are provided with their respective fuses. If a word line and a bit line are short-circuited, the fuse of the precharge circuit corresponding to the defective pair of big lines may be melted for disconnection so that the defective pair of bit lines are not precharged to the intermediate potential. However, since each of the precharge circuits is disposed between two bit lines forming a pair and a sense amplifier and like elements are placed around them, it is spatially difficult to dispose a fuse in or around each of the precharge circuits.
To overcome the difficulty, there has conventionally been proposed a semiconductor memory device in Which a plurality of precharge power-source lines are assigned individually to a plurality of precharge circuits and fuses are disposed in the respective precharge power-source lines. There has been disclosed a prior art which uses the above method to reduce the leakage current in a DRAM on standby (ISSCC DIGEST OF TECHNICAL PAPERS 93 (1993), pp. 48-49).
The prior art is shown in FIGS. 11 and 12, in which a plurality of memory cell blocks 500 . . . are formed (in FIG. 12, only one memory cell block is shown) by dividing a single memory cell array, while sense amplifier blocks 700 . . . are disposed on one side of the corresponding memory cell blocks 500 . . . In each of the sense amplifier blocks 700 . . . , precharge circuits which are equal in number to the pairs of bit lines in the corresponding memory cell block 500 are provided in the direction in which the bit lines extend so that each of the precharge circuits precharges the corresponding pair of bit lines to a specified potential. In addition, as a redundant substitution system in case of a short circuit between a bit line and a word line, there are provided redundant memory cell blocks 600 and redundant sense amplifier blocks 800 (only one redundant memory cell block and only one redundant sense amplifier block are shown in FIG. 12). The redundant sense amplifier blocks 800 are provided on one side of the corresponding redundant memory cell blocks 600. A pair of precharge power-source lines 650a and 650s are provided for each of the above regular precharge sense amplifier blocks 700 and for each of the redundant sense amplifier blocks 800. There is also provided a precharge potential supply line 670 for supplying a potential to the power-source lines 650a and 650s. Between each of the power-source lines 650a ... and the precharge potential supply line 670 are provided power switches 660a . . . and 660s . . . If any one bit line in any memory cell block 500 is short-circuited with a word line, the power switch 660a corresponding to the memory cell block 500 containing the defective bit line is disconnected so as to inhibit the precharging of the memory cell block 500 containing the defective bit line, thus preventing the flow of the leakage current. On the other hand, the power switch 660s corresponding to the redundant memory cell block 600 is closed so as to enable the precharging of the redundant memory cell block 600, thereby substituting the above memory cell block 500 containing the defective bit line with the redundant memory cell block 600.
However, the above prior art has the following drawback. That is, if any one bit line in any one memory cell block 500 is short-circuited with a word line, the power switch 660a for the precharge power-source line 650a corresponding to the memory cell block 500 is opened, with the result that the sense amplifier block 700 corresponding to the precharge power-source line 650a is not supplied with the precharge potential. Consequently, in the above memory cell block 500 containing the defective bit line, the majority of normal pairs of bit lines and word lines cannot be used until the whose memory cell block 500 is substituted with the redundant memory cell block 600. Therefore, it is necessary to design the redundant memory cell block 600 and the regular memory cell block 500 in equal size, which increases the chip area disadvantageously.
The present inventors have also found that, even if the above precharge power-source line 650a is opened with the power switch 660a, the standby current is allowed to flow from another power-source line to a ground line via the defective bit line and word line. The flow of the standby current is shown in FIG. 13.
In FIG. 13 are shown: two bit lines BL and BL/ forming a pair; a word line WL; a precharge circuit 800 consisting of three transistors for connecting the two bit lines BL and /BL; a precharge power-source line 810 for supplying a specified potential to the precharge circuit 800; an equalize signal line 820 for turning ON the three transistors of the above precharge circuit 800; a sense amplifier 850 consisting of two P-channel transistors TP connected in series for connecting the pair of bit lines BL and /BL and of two N-channel transistors TN connected in series for connecting the pair of bit lines BL and /BL, so that a common source line SP is connected to the connecting point between the above two P-channel transistors TP and another common source line AN is connected to the connecting point between the above two N-channel transistors TN; a common-source-line equalize circuit 860 consisting of three transistors for connecting the above two common source lines SP and SN and equalizing them to a power-source potential 1/2.multidot.Vcc; a potential supply circuit 870 for setting the common source line SP at a power-source potential Vcc and setting the common source line SN at the ground potential Vss; an equalize signal eq outputted to the common-source-line equalize circuit 860; and an inverted signal/eq of the above equalize signal eq, which is outputted to the potential supply circuit 870.
A description will be given to the operation of the above structure of FIG. 13 with reference to the individual signal waveforms shown in FIG. 14.
During the operation of precharging the pairs of bit lines, a signal EQ on the equalize signal line 820 is activated so as to precharge the bit lines BL and /BL to a specified potential (1/2.multidot.Vcc), while the equalize signal eq is activated so as to equalize the common source lines SP and SN to a specified potential (1/2.multidot.Vcc), thereby placing the sense amplifier 850 on standby. During the operation of amplifying the pair of bit lines BL and /BL, the signal EQ on the equalize signal line 820 and the equalize signal eq are inactivated, while the inverted signal /eq of the equalize signal eq are activated. As a result, a slight potential difference is caused between the pair of bit lines BL and /BL by the selected word line WL, which is detected and amplified by the sense amplifier 850.
With the above prior art shown in FIG. 13, if there is a short-circuit (represented by "R" in FIG. 13) between one bit line BL and a word line WL, for example, the potential on the above defective bit line BL becomes lower than the precharge potential 1/2.multidot.Vcc during the operation of precharging the pairs of bit lines. Accordingly, the slight potential difference is caused between the pair of b it lines BL and BL/, while the gate potential in the P-channel transistor TP positioned below the sense amplifier 850 becomes lower than the above precharge potential 1/2.multidot.Vcc. Consequently, if the gate-source potential in the P-channel transistor TP surpasses the threshold voltage thereof, the P-channel transistor TP is turned ON so that the standby current is allowed to flow from the common source line SP to the other bit line /BL via the above transistor TP on the lower position that has been turned ON. As a result, the N-channel transistor TN on the upper position is turned ON so that the standby current is allowed to flow from the power source of 1/2.multidot.Vcc toward the ground via the common-source-line equalize circuit 860, the transistor TN on the upper position that has been turned ON, the above defective bit line BL, and the word line WL.